This invention relates to apparatus for transferring data from one electronic device to another, and has particular relation to such apparatus when the devices are asynchonous and remote from each other.
When two devices are operating at different speeds, it makes no sense for the device which is sending data (sender) to delay in sending the data until the device which is receiving the data (receiver) is ready to receive it. Instead, the data is placed in a buffer by the sender, which works on a first-in-first-out (FIFO) basis. The receiver then requests and gets the oldest piece of data from the FIFO, rather than communicating directly with the sender. This allows additional pieces of data to be placed in the FIFO by the sender.
As long as the average operation speed of the sender is about the same as that of the receiver, both devices may operate at top speed. When the sender produces a sudden spurt of data, it may output it to the FIFO, making it fuller, without waiting for the receiver to accept the data. Likewise, when the sender is occupied obtaining the next piece of data, the receiver may consume the data in the FIFO, making it emptier, and need not delay this data consumption until the sender has sent the data. Only if the FIFO is empty does the receiver have to wait until the sender puts the next piece of data into the FIFO. A READY signal is used to communicate to the receiver when valid data is available.
The buffer (FIFO) could have significant access time delays in relation to the receiver data transfer cycle.
Since in this case the data transfer time includes the FIFO access time (i.e., the time it takes the receiver to read data out of the FIFO), a speed penalty of additional wait states for each data transfer may be incurred if the FIFO access time, plus the propagation delays, is longer than the minimum data transfer cycle time. This is not acceptable for high speed operations where additional wait states for every data transfer can not be tolerated.
The data transfer time can be speeded up by reading data out of the FIFO before the data transfer request and placing it in a pipeline register. This allows the receiver to get the data from the pipeline register immediately upon request without having to wait for the FIFO access time needed to read the data out.
While the pipeline register speeds up the typical data transfer cycle, three special cases need to be considered. The first case is when the pipeline is empty, i.e., the pipeline register does not have valid data. This happens when the system is first initialized or when the FIFO has been emptied and valid data has been read out of the pipeline register.
In this case the receiver will need to make two data transfers to get valid data. The first data transfer sends invalid data from the pipeline register to the receiver, while valid data is read out of the FIFO and is loaded into the pipeline register. On the second data transfer, this valid data is moved from pipeline register to the receiver. This double data transfer to get the first valid data is referred to as "filling the pipeline."
The prior art has no way to know when this double request should be made. It is possible to encode the invalid data so as to indicate to the receiver that the receiver should discard the invalid data and make another data transfer request. This requires that every piece of data be checked by the receiver for validity. Such checking is generally time consuming and often impossible for high speed operation.
The second case is the ordinary case. The pipeline register is full when it is read out to the receiver, and the FIFO has additional data to read into the pipeline register, i.e., the pipeline register remains full. The only special apparatus needed for this second case is whatever is required for a smooth transition to (or from) it and either the first or the third case.
The third case that the receiver or data transfer logic will need to check for is when the FIFO initially goes empty (is emptied of any valid data). In this case even though the FIFO has no valid words, there is still one remaining valid word in the pipeline register. The receiver or data transfer logic will need to allow one last transfer to occur from the pipeline register to the receiver even though no valid data is available in the FIFO. This last data transfer is referred to as "emptying the pipeline."